{"@context":"http://iiif.io/api/presentation/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/manifest.json","@type":"sc:Manifest","label":"Enhancing Power and Signal Integrity in Three-Dimensional Integrated Circuits","metadata":[{"label":"dc.description.sponsorship","value":"This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree."},{"label":"dc.format","value":"Monograph"},{"label":"dc.format.medium","value":"Electronic Resource"},{"label":"dc.identifier.uri","value":"http://hdl.handle.net/11401/77490"},{"label":"dc.language.iso","value":"en_US"},{"label":"dc.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.abstract","value":"Three-dimensional (3D) integration has emerged as an enabling technology for integrated circuits (ICs) in the interconnect-centric design era, where the interconnects have become a bottleneck for the overall system performance. With 3D integration technology, multiple planar dies are stacked vertically while the communication among different dies is achieved by low impedance vertical connections such as through silicon vias (TSVs) or monolithic inter-tier vias (MIVs). Due to the unique characteristics of 3D ICs, various challenges exist in the fabrication, design and testing of 3D integrated systems. The research work proposed in this dissertation is focused on 3D design methodologies with emphasis on power and signal integrity. Specifically, to reliably deliver the power supply voltage to each circuit module within a 3D system, i.e., maintaining system-wide power integrity, the power distribution network in 3D ICs should be carefully designed with specific design considerations different from traditional 2D ICs. In this dissertation, two critical issues about the power distribution network are investigated to improve the power integrity of TSV-based 3D ICs. First, novel design topologies and analytic expressions are proposed for the physical implementation of power gating in 3D ICs. Power gating is an existing and effective low power design method to reduce leakage power consumption. It is demonstrated that the proposed methodology can effectively improve power integrity for 3D ICs with power gating. Alternatively, the efficacy of decoupling capacitors, which are intentional capacitors placed to reduce power supply noise, can be degraded due to power gating in 3D ICs. A reconfigurable decoupling capacitor topology that dynamically configures the connectivity of decoupling capacitors is investigated to achieve better utilization of the decoupling capacitors and further enhance power integrity of 3D ICs with power gating. In addition, to provide a fast yet accurate estimation of power supply noise, an analytic model and closed-form expressions are proposed, exhibiting significant improvement over existing analytical models for nanoscale ICs with fast transitions. In addition to power integrity, TSV-based 3D ICs also introduce distinctive signal integrity issues. Electrical noise can couple from the TSVs into the silicon substrate of a die, which can disturb the operation of the active devices within the die. A methodology is developed to characterize the TSV induced noise coupling in 3D ICs. Design guidelines are also proposed based on the noise characterization results to improve signal integrity within 3D ICs. Finally, the monolithic 3D integration technology based on MIVs (rather than TSVs) is investigated. To evaluate the benefits of MIV-based 3D ICs, Mono3D, a standard cell library for transistor-level monolithic 3D ICs, is developed in 45 nm CMOS technology. A complete back-end physical design flow utilizing the proposed Mono3D library is also demonstrated. As an example, a benchmark circuit is designed from gate-level netlist to physical layout using the Mono3D to evaluate the performance and power consumption of MIV-based 3D ICs."},{"label":"dcterms.available","value":"2017-09-20T16:52:48Z"},{"label":"dcterms.contributor","value":"Salman, Emre"},{"label":"dcterms.creator","value":"Wang, Hailang"},{"label":"dcterms.dateAccepted","value":"2017-09-20T16:52:48Z"},{"label":"dcterms.dateSubmitted","value":"2017-09-20T16:52:48Z"},{"label":"dcterms.description","value":"Department of Electrical Engineering."},{"label":"dcterms.extent","value":"197 pg."},{"label":"dcterms.format","value":"Application/PDF"},{"label":"dcterms.identifier","value":"http://hdl.handle.net/11401/77490"},{"label":"dcterms.issued","value":"2016-12-01"},{"label":"dcterms.language","value":"en_US"},{"label":"dcterms.provenance","value":"Made available in DSpace on 2017-09-20T16:52:48Z (GMT). No. of bitstreams: 1\nWang_grad.sunysb_0771E_12753.pdf: 2003688 bytes, checksum: 059dbed1b9d0fe18c2b0808071e8eb2a (MD5)\n  Previous issue date:    1"},{"label":"dcterms.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.subject","value":"Electrical engineering"},{"label":"dcterms.title","value":"Enhancing Power and Signal Integrity in Three-Dimensional Integrated Circuits"},{"label":"dcterms.type","value":"Dissertation"},{"label":"dc.type","value":"Dissertation"}],"description":"This manifest was generated dynamically","viewingDirection":"left-to-right","sequences":[{"@type":"sc:Sequence","canvases":[{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json","@type":"sc:Canvas","label":"Page 1","height":1650,"width":1275,"images":[{"@type":"oa:Annotation","motivation":"sc:painting","resource":{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/43%2F26%2F51%2F43265130538274775185422684000589143461/full/full/0/default.jpg","@type":"dctypes:Image","format":"image/jpeg","height":1650,"width":1275,"service":{"@context":"http://iiif.io/api/image/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/43%2F26%2F51%2F43265130538274775185422684000589143461","profile":"http://iiif.io/api/image/2/level2.json"}},"on":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json"}]}]}]}