{"@context":"http://iiif.io/api/presentation/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/manifest.json","@type":"sc:Manifest","label":"Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability","metadata":[{"label":"dc.description.sponsorship","value":"This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree."},{"label":"dc.format","value":"Monograph"},{"label":"dc.format.medium","value":"Electronic Resource"},{"label":"dc.identifier.uri","value":"http://hdl.handle.net/11401/77481"},{"label":"dc.language.iso","value":"en_US"},{"label":"dc.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.abstract","value":"A novel glitch-free integrated clock gating (ICG) cell is developed and demonstrated in 45 nm CMOS technology. The proposed cell is more reliable as it produces an uninterrupted gated clock signal in cases where glitches occur in the enable signal during clock transitions. A detailed comparison of the proposed cell with the existing integrated clock gating cells is also presented. Glitch-free operation (and therefore high reliability) is achieved at the expense of larger power and delay, as quantified for 45 nm CMOS technology. Several design issues and different glitch characteristics are also discussed. The proposed ICG cell is shown to be highly applicable to dual edge triggered flip- flops where existing ICGs fail if there are glitches in the enable during clock transitions."},{"label":"dcterms.available","value":"2017-09-20T16:52:47Z"},{"label":"dcterms.contributor","value":"Hong, Sangjin."},{"label":"dcterms.creator","value":"Noor, Tasnuva"},{"label":"dcterms.dateAccepted","value":"2017-09-20T16:52:47Z"},{"label":"dcterms.dateSubmitted","value":"2017-09-20T16:52:47Z"},{"label":"dcterms.description","value":"Department of Electrical Engineering."},{"label":"dcterms.extent","value":"44 pg."},{"label":"dcterms.format","value":"Monograph"},{"label":"dcterms.identifier","value":"http://hdl.handle.net/11401/77481"},{"label":"dcterms.issued","value":"2016-12-01"},{"label":"dcterms.language","value":"en_US"},{"label":"dcterms.provenance","value":"Made available in DSpace on 2017-09-20T16:52:47Z (GMT). No. of bitstreams: 1\nNoor_grad.sunysb_0771M_12887.pdf: 1963312 bytes, checksum: 9aee9c715cb3b192d5a1ea24130d24bd (MD5)\n  Previous issue date:    1"},{"label":"dcterms.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.subject","value":"Clock Gating, Dual Edge Triggered Flip-flop, Integrated Circuit Design, Integrated Clock Gating Cell, Low Power Design, VLSI"},{"label":"dcterms.title","value":"Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability"},{"label":"dcterms.type","value":"Thesis"},{"label":"dc.type","value":"Thesis"}],"description":"This manifest was generated dynamically","viewingDirection":"left-to-right","sequences":[{"@type":"sc:Sequence","canvases":[{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json","@type":"sc:Canvas","label":"Page 1","height":1650,"width":1275,"images":[{"@type":"oa:Annotation","motivation":"sc:painting","resource":{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/27%2F75%2F11%2F2775112687846163482658997222329428474/full/full/0/default.jpg","@type":"dctypes:Image","format":"image/jpeg","height":1650,"width":1275,"service":{"@context":"http://iiif.io/api/image/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/27%2F75%2F11%2F2775112687846163482658997222329428474","profile":"http://iiif.io/api/image/2/level2.json"}},"on":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json"}]}]}]}