{"@context":"http://iiif.io/api/presentation/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/manifest.json","@type":"sc:Manifest","label":"Parallel and Flexible Hardware Implementation of Fletcher Checksum","metadata":[{"label":"dc.description.sponsorship","value":"This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree."},{"label":"dc.format","value":"Monograph"},{"label":"dc.format.medium","value":"Electronic Resource"},{"label":"dc.identifier.uri","value":"http://hdl.handle.net/11401/77480"},{"label":"dc.language.iso","value":"en_US"},{"label":"dc.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.abstract","value":"Checksums are utilized in many contexts such as communications, storage and reliable processing. The balance between checksum strength, implementation cost and obtained throughput often pose a challenge for present day system designers. In this research we propose two new methods for implementing the Fletcher Checksum (FC) in a parallelized context. We determined an extended parallel definition from the original FC and applied it to two different hardware implementation approaches. We then created a generator that would automatically output parameterized designs. We controlled the input word length, number of parallel inputs and architecture of the designs, and we then synthesized these designs for FPGA and ASIC. Our results show that parallelization of FC is feasible and the system throughput is proportional to the cost defined by resources used, area and power consumption. In our results, we demonstrate designs with throughput up to 375 Gbits/sec in ASIC and up to 110 Gbits/sec in FPGA, depending on the specific parameters."},{"label":"dcterms.available","value":"2017-09-20T16:52:47Z"},{"label":"dcterms.contributor","value":"Milder, Peter"},{"label":"dcterms.creator","value":"Mera Collantes, Maria Isabel"},{"label":"dcterms.dateAccepted","value":"2017-09-20T16:52:47Z"},{"label":"dcterms.dateSubmitted","value":"2017-09-20T16:52:47Z"},{"label":"dcterms.description","value":"Department of Electrical Engineering."},{"label":"dcterms.extent","value":"36 pg."},{"label":"dcterms.format","value":"Monograph"},{"label":"dcterms.identifier","value":"http://hdl.handle.net/11401/77480"},{"label":"dcterms.issued","value":"2014-12-01"},{"label":"dcterms.language","value":"en_US"},{"label":"dcterms.provenance","value":"Made available in DSpace on 2017-09-20T16:52:47Z (GMT). No. of bitstreams: 1\nMeraCollantes_grad.sunysb_0771M_11920.pdf: 556387 bytes, checksum: d002ccbf08485e00aa922dd31b692f03 (MD5)\n  Previous issue date:    1"},{"label":"dcterms.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.subject","value":"asic, checksum, fpga, hardware, implementation, parallel"},{"label":"dcterms.title","value":"Parallel and Flexible Hardware Implementation of Fletcher Checksum"},{"label":"dcterms.type","value":"Thesis"},{"label":"dc.type","value":"Thesis"}],"description":"This manifest was generated dynamically","viewingDirection":"left-to-right","sequences":[{"@type":"sc:Sequence","canvases":[{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json","@type":"sc:Canvas","label":"Page 1","height":1650,"width":1275,"images":[{"@type":"oa:Annotation","motivation":"sc:painting","resource":{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/63%2F63%2F42%2F63634210522066819842919173185441789222/full/full/0/default.jpg","@type":"dctypes:Image","format":"image/jpeg","height":1650,"width":1275,"service":{"@context":"http://iiif.io/api/image/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/63%2F63%2F42%2F63634210522066819842919173185441789222","profile":"http://iiif.io/api/image/2/level2.json"}},"on":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json"}]}]}]}