{"@context":"http://iiif.io/api/presentation/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/manifest.json","@type":"sc:Manifest","label":"Analog circuit design knowledge mining and circuit causal information modeling","metadata":[{"label":"dc.description.sponsorship","value":"This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree."},{"label":"dc.format","value":"Monograph"},{"label":"dc.format.medium","value":"Electronic Resource"},{"label":"dc.identifier.uri","value":"http://hdl.handle.net/11401/77440"},{"label":"dc.language.iso","value":"en_US"},{"label":"dc.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.abstract","value":"This thesis proposes novel approaches for analog circuit design knowledge mining and circuit causal information modeling. In particular, knowledge mining discovers and decomposes analog circuit design knowledge into three components: (1) a conceptual hierarchy for a group of circuit topologies, (2) circuits' performance capabilities (including trade-offs and bottlenecks), and (3) circuits' design causal reasoning strategies. Causal reasoning strategies lead to the development of reasoning-based topology synthesis and design verification, thus bring new perspective to existing approaches. Extended from performance capabilities, the thesis proposes circuit causal information modeling, which models relations of parameters deciding circuit performance attributes and coupling with other parameters. Different causal information measure reveals ordered parameter sequence and circuit sizing strategy."},{"label":"dcterms.available","value":"2017-09-20T16:52:41Z"},{"label":"dcterms.contributor","value":"Stanacevic, Milutin"},{"label":"dcterms.creator","value":"Jiao, Fanshu"},{"label":"dcterms.dateAccepted","value":"2017-09-20T16:52:41Z"},{"label":"dcterms.dateSubmitted","value":"2017-09-20T16:52:41Z"},{"label":"dcterms.description","value":"Department of Electrical Engineering"},{"label":"dcterms.extent","value":"196 pg."},{"label":"dcterms.format","value":"Application/PDF"},{"label":"dcterms.identifier","value":"http://hdl.handle.net/11401/77440"},{"label":"dcterms.issued","value":"2016-12-01"},{"label":"dcterms.language","value":"en_US"},{"label":"dcterms.provenance","value":"Made available in DSpace on 2017-09-20T16:52:41Z (GMT). No. of bitstreams: 1\nJiao_grad.sunysb_0771E_13133.pdf: 1226699 bytes, checksum: b8eab4c4c221021d4a0df39fe142b25d (MD5)\n  Previous issue date:    1"},{"label":"dcterms.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.subject","value":"Analog circuit design automation, Causal information modeling, Design knowledge mining, Design verification, Topology synthesis"},{"label":"dcterms.title","value":"Analog circuit design knowledge mining and circuit causal information modeling"},{"label":"dcterms.type","value":"Dissertation"},{"label":"dc.type","value":"Dissertation"}],"description":"This manifest was generated dynamically","viewingDirection":"left-to-right","sequences":[{"@type":"sc:Sequence","canvases":[{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json","@type":"sc:Canvas","label":"Page 1","height":1650,"width":1275,"images":[{"@type":"oa:Annotation","motivation":"sc:painting","resource":{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/94%2F93%2F76%2F94937606163490489841274017894477350454/full/full/0/default.jpg","@type":"dctypes:Image","format":"image/jpeg","height":1650,"width":1275,"service":{"@context":"http://iiif.io/api/image/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/94%2F93%2F76%2F94937606163490489841274017894477350454","profile":"http://iiif.io/api/image/2/level2.json"}},"on":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json"}]}]}]}