{"@context":"http://iiif.io/api/presentation/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/manifest.json","@type":"sc:Manifest","label":"Power Distribution in 3-D Processor-Memory Stacks","metadata":[{"label":"dc.description.sponsorship","value":"This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree."},{"label":"dc.format","value":"Monograph"},{"label":"dc.format.medium","value":"Electronic Resource"},{"label":"dc.identifier.uri","value":"http://hdl.handle.net/1951/57605"},{"label":"dc.language.iso","value":"en_US"},{"label":"dc.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.abstract","value":"Three primary techniques for manufacturing through silicon vias (TSVs), viafirst,\nvia-middle, and via-last, have been analyzed and compared to distribute power\nin a three-dimensional (3-D) processor-memory system with nine planes. Due to\ndistinct fabrication techniques, these TSV technologies require significantly different\ndesign constraints, as investigated in this work. A valid design space that\nsatisfies the peak power supply noise while minimizing area overhead is identified\nfor each technology. It is demonstrated that the area overhead of a power distribution\nnetwork with via-first TSVs is approximately 9% as compared to less than\n2% in via-middle and via-last technologies. Despite this drawback, a via-first based\npower network is typically overdamped and the issue of resonance is alleviated. A\nvia-last based power network, however, exhibits a relatively low damping factor and\nthe peak noise is highly sensitive to number of TSVs and decoupling capacitance."},{"label":"dcterms.available","value":"2015-04-24T14:45:51Z"},{"label":"dcterms.contributor","value":"Salman, Emre"},{"label":"dcterms.creator","value":"Satheesh, Suhas M."},{"label":"dcterms.dateAccepted","value":"2012-10-10T16:17:28Z"},{"label":"dcterms.dateSubmitted","value":"2012-10-10T16:17:28Z"},{"label":"dcterms.description","value":"Department of Electrical Engineering."},{"label":"dcterms.format","value":"Application/PDF"},{"label":"dcterms.identifier","value":"http://hdl.handle.net/1951/57605"},{"label":"dcterms.issued","value":"2012-05-01"},{"label":"dcterms.language","value":"en_US"},{"label":"dcterms.provenance","value":"Made available in DSpace on 2012-10-10T16:17:28Z (GMT). No. of bitstreams: 1\nSatheesh_grad.sunysb_0771M_10918.pdf: 1699631 bytes, checksum: 450f6f19e09838dcb55e1e678c7ad54c (MD5)\n  Previous issue date: 2012-05-01"},{"label":"dcterms.publisher","value":"The Graduate School, Stony Brook University: Stony Brook, NY."},{"label":"dcterms.subject","value":"3-D IC, Decoupling capacitor, Peak noise, Power delivery, Processor-memory, TSV"},{"label":"dcterms.title","value":"Power Distribution in 3-D Processor-Memory Stacks"},{"label":"dcterms.type","value":"Thesis"},{"label":"dc.type","value":"Thesis"}],"description":"This manifest was generated dynamically","viewingDirection":"left-to-right","sequences":[{"@type":"sc:Sequence","canvases":[{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json","@type":"sc:Canvas","label":"Page 1","height":1650,"width":1275,"images":[{"@type":"oa:Annotation","motivation":"sc:painting","resource":{"@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/10%2F59%2F77%2F105977200922583058204199024541727563767/full/full/0/default.jpg","@type":"dctypes:Image","format":"image/jpeg","height":1650,"width":1275,"service":{"@context":"http://iiif.io/api/image/2/context.json","@id":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/10%2F59%2F77%2F105977200922583058204199024541727563767","profile":"http://iiif.io/api/image/2/level2.json"}},"on":"https://repo.library.stonybrook.edu/cantaloupe/iiif/2/canvas/page-1.json"}]}]}]}